One of the challenges device designers face when attempting to form certain types of transistor devices using III-V compound semiconductors (e.g. gallium arsenide (GaAs), indium antimonide (InSb), etc) on a silicon substrate pertains to what is known as parallel conduction in the silicon substrate. Parallel conduction occurs when there are undesirable conduction paths other than between a transistor's source and drain regions, e.g. between the transistor and the silicon substrate. In addition, so-called lattice mismatches between a film of larger lattice constant relative to which the transistor is formed and the silicon substrate can lead to problematic device operation.